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stm32 /stm32g0 /STM32G081 /RCC /APBRSTR2

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Interpret as APBRSTR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYSCFGRST)SYSCFGRST 0 (TIM1RST)TIM1RST 0 (SPI1RST)SPI1RST 0 (USART1RST)USART1RST 0 (TIM14RST)TIM14RST 0 (TIM15RST)TIM15RST 0 (TIM16RST)TIM16RST 0 (TIM17RST)TIM17RST 0 (ADCRST)ADCRST

Description

APB peripheral reset register 2

Fields

SYSCFGRST

SYSCFG, COMP and VREFBUF reset
TIM1RST

TIM1 timer reset
SPI1RST

SPI1 reset
USART1RST

USART1 reset
TIM14RST

TIM14 timer reset
TIM15RST

TIM15 timer reset
TIM16RST

TIM16 timer reset
TIM17RST

TIM17 timer reset
ADCRST

ADC reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32