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stm32 /stm32g0 /STM32G0B0 /RCC /CCIPR2

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Interpret as CCIPR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2S1SEL 0I2S2SEL 0USBSEL

Description

Peripherals independent clock configuration register 2

Fields

I2S1SEL

2S1SEL
I2S2SEL

I2S2SEL
USBSEL

USBSEL

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32