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stm32 /stm32g0 /STM32G0B0 /TIM1 /TIM1_OR1

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Interpret as TIM1_OR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)OCREF_CLR

OCREF_CLR=B_0x0

Description

option register 1

Fields

OCREF_CLR

Ocref_clr source selection This bit selects the ocref_clr input source.

0 (B_0x0): COMP1 output is connected to the OCREF_CLR input

1 (B_0x1): COMP2 output is connected to the OCREF_CLR input

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32