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stm32 /stm32g0 /STM32G0B0 /TIM3 /AF1

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Interpret as AF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ETRSEL

ETRSEL=B_0x0

Description

TIM alternate function option register 1

Fields

ETRSEL

ETR source selection These bits select the ETR input source. Others: Reserved

0 (B_0x0): ETR legacy mode

1 (B_0x1): COMP1

2 (B_0x2): COMP2

3 (B_0x3): LSE

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32