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stm32 /stm32g0 /STM32G0B1 /FLASH /ACR

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Interpret as ACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LATENCY 0 (PRFTEN)PRFTEN 0 (ICEN)ICEN 0 (ICRST)ICRST 0 (EMPTY)EMPTY 0 (DBG_SWEN)DBG_SWEN

Description

Access control register

Fields

LATENCY

Latency
PRFTEN

Prefetch enable
ICEN

Instruction cache enable
ICRST

Instruction cache reset
EMPTY

Flash User area empty
DBG_SWEN

Debug access software enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32