Regviz

stm32 /stm32g4 /STM32G473 /IWDG /RLR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RLR

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https://regviz.com/r/stm32/stm32f4/STM32F412/IWDG/RLR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RL

Description

Reload register

Fields

RL

Watchdog counter reload value

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32