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stm32 /stm32g4 /STM32G483 /GPIOC /BRR

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Interpret as BRR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BR0)BR0 0 (BR1)BR1 0 (BR2)BR2 0 (BR3)BR3 0 (BR4)BR4 0 (BR5)BR5 0 (BR6)BR6 0 (BR7)BR7 0 (BR8)BR8 0 (BR9)BR9 0 (BR10)BR10 0 (BR11)BR11 0 (BR12)BR12 0 (BR13)BR13 0 (BR14)BR14 0 (BR15)BR15

Description

GPIO port bit reset register

Fields

BR0

Port Reset bit
BR1

Port Reset bit
BR2

Port Reset bit
BR3

Port Reset bit
BR4

Port Reset bit
BR5

Port Reset bit
BR6

Port Reset bit
BR7

Port Reset bit
BR8

Port Reset bit
BR9

Port Reset bit
BR10

Port Reset bit
BR11

Port Reset bit
BR12

Port Reset bit
BR13

Port Reset bit
BR14

Port Reset bit
BR15

Port Reset bit

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32