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stm32 /stm32g4 /STM32G483 /TIM1 /ECR

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Interpret as ECR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IE)IE 0IDIR 0IBLK 0 (FIDX)FIDX 0IPOS 0PW0PWPRSC

Description

DMA control register

Fields

IE

Index Enable
IDIR

Index Direction
IBLK

Index Blanking
FIDX

First Index
IPOS

Index Positioning
PW

Pulse width
PWPRSC

Pulse Width prescaler

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32