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stm32 /stm32g4 /STM32G491 /ADC1 /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ROVSE)ROVSE 0 (JOVSE)JOVSE 0OVSR0OVSS0 (TROVS)TROVS 0 (ROVSM)ROVSM 0 (GCOMP)GCOMP 0 (SWTRIG)SWTRIG 0 (BULB)BULB 0 (SMPTRIG)SMPTRIG

Description

configuration register

Fields

ROVSE

DMAEN
JOVSE

DMACFG
OVSR

RES
OVSS

ALIGN
TROVS

Triggered Regular Oversampling
ROVSM

EXTEN
GCOMP

GCOMP
SWTRIG

SWTRIG
BULB

BULB
SMPTRIG

SMPTRIG

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32