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stm32 /stm32g4 /STM32G491 /TIM2 /AF2

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Interpret as AF2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BKINE)BKINE 0 (BK2CMP1E)BK2CMP1E 0 (BK2CMP2E)BK2CMP2E 0 (BK2CMP3E)BK2CMP3E 0 (BK2CMP4E)BK2CMP4E 0 (BK2CMP5E)BK2CMP5E 0 (BK2CMP6E)BK2CMP6E 0 (BK2CMP7E)BK2CMP7E 0 (BK2INP)BK2INP 0 (BK2CMP1P)BK2CMP1P 0 (BK2CMP2P)BK2CMP2P 0 (BK2CMP3P)BK2CMP3P 0 (BK2CMP4P)BK2CMP4P 0OCRSEL

Description

TIM alternate function option register 2

Fields

BKINE

BRK BKIN input enable
BK2CMP1E

BRK2 COMP1 enable
BK2CMP2E

BRK2 COMP2 enable
BK2CMP3E

BRK2 COMP3 enable
BK2CMP4E

BRK2 COMP4 enable
BK2CMP5E

BRK2 COMP5 enable
BK2CMP6E

BRK2 COMP6 enable
BK2CMP7E

BRK2 COMP7 enable
BK2INP

BRK2 BKIN input polarity
BK2CMP1P

BRK2 COMP1 input polarity
BK2CMP2P

BRK2 COMP2 input polarity
BK2CMP3P

BRK2 COMP3 input polarity
BK2CMP4P

BRK2 COMP4 input polarity
OCRSEL

OCREF_CLR source selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32