Regviz

stm32 /stm32g4 /STM32G4A1 /ADC1 /DR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DR

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https://regviz.com/r/stm32/stm32g4/STM32G431/ADC1/DR#0x0

31282724232019161512118743000000000000000000000000000000000000000000RDATA

Description

regular Data Register

Fields

RDATA

Regular Data converted

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32