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stm32 /stm32g4 /STM32G4A1 /DAC1 /DAC_SHRR

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Interpret as DAC_SHRR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TREFRESH10TREFRESH2

Description

DAC Sample and Hold refresh time register

Fields

TREFRESH1

DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI
TREFRESH2

DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32