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stm32 /stm32g4 /STM32GBK1CBT6 /DMA1 /IFCR

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Interpret as IFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GIF1)GIF1 0 (TCIF1)TCIF1 0 (HTIF1)HTIF1 0 (TEIF1)TEIF1 0 (GIF2)GIF2 0 (TCIF2)TCIF2 0 (HTIF2)HTIF2 0 (TEIF2)TEIF2 0 (GIF3)GIF3 0 (TCIF3)TCIF3 0 (HTIF3)HTIF3 0 (TEIF3)TEIF3 0 (GIF4)GIF4 0 (TCIF4)TCIF4 0 (HTIF4)HTIF4 0 (TEIF4)TEIF4 0 (GIF5)GIF5 0 (TCIF5)TCIF5 0 (HTIF5)HTIF5 0 (TEIF5)TEIF5 0 (GIF6)GIF6 0 (TCIF6)TCIF6 0 (HTIF6)HTIF6 0 (TEIF6)TEIF6 0 (GIF7)GIF7 0 (TCIF7)TCIF7 0 (HTIF7)HTIF7 0 (TEIF7)TEIF7 0 (GIF8)GIF8 0 (TCIF8)TCIF8 0 (HTIF8)HTIF8 0 (TEIF8)TEIF8

Description

DMA interrupt flag clear register

Fields

GIF1

GIF1
TCIF1

TCIF1
HTIF1

HTIF1
TEIF1

TEIF1
GIF2

GIF2
TCIF2

TCIF2
HTIF2

HTIF2
TEIF2

TEIF2
GIF3

GIF3
TCIF3

TCIF3
HTIF3

HTIF3
TEIF3

TEIF3
GIF4

GIF4
TCIF4

TCIF4
HTIF4

HTIF4
TEIF4

TEIF4
GIF5

GIF5
TCIF5

TCIF5
HTIF5

HTIF5
TEIF5

TEIF5
GIF6

GIF6
TCIF6

TCIF6
HTIF6

HTIF6
TEIF6

TEIF6
GIF7

GIF7
TCIF7

TCIF7
HTIF7

HTIF7
TEIF7

TEIF7
GIF8

GIF8
TCIF8

TCIF8
HTIF8

HTIF8
TEIF8

TEIF8

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32