Regviz

stm32 /stm32g4 /STM32GBK1CBT6 /TIM15 /TISEL

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Interpret as TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TI1SEL0TI2SEL

Description

TIM timer input selection register

Fields

TI1SEL

TI1[0] to TI1[15] input selection
TI2SEL

TI2[0] to TI2[15] input selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32