stm32 /stm32h5 /STM32H503 /I3C1 /I3C_CFGR

I3C enable (whatever I3C is acting as controller/target)

• Except registers, the peripheral is under reset (a.k.a. partial reset).
• Before clearing EN, when I3C is acting as a controller, all the possible target requests must be disabled using DISEC CCC.
• When I3C is acting as a target, software should not disable the I3C, unless a partial reset is needed. In this state, some register fields can not be modified (like CRINIT, HKSDAEN for the I3C_CFGR)

0 (B_0x0): I3C is disabled

1 (B_0x1): I3C is enabled

initial controller/target role This bit can be modified only when I3C_CFGR.EN = 0. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as an I3C target. I3C does not drive SCL line and does not enable SDA pull-up, until it eventually acquires the controller role. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as a controller. It has the I3C controller role, so drives SCL line and enables SDA pull-up, until it eventually offers the controller role to an I3C secondary controller.

0 (B_0x0): target role

1 (B_0x1): controller role

no arbitrable header after a START (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame.

• The target address is emitted directly after a START in case of a legacy I2C message or an I3C SDR private read/write message.
• This is a more performing option (when is useless the emission of the 0x7E arbitrable header), but this is to be used only when the controller is sure that the addressed target device can not emit concurrently an IBI or a controller-role request (to insure no misinterpretation and no potential conflict between the address emitted by the controller in open-drain mode and the same address a target device can emit after a START, for IBI or MR).

0 (B_0x0): An arbitrable header (7’h7E + RnW=0) is emitted after a START and before a legacy I2C message or an I3C SDR private read/write message (default).

1 (B_0x1): No arbitrable header

HDR reset pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame.

0 (B_0x0): standard STOP emitted at the end of a frame

1 (B_0x1): HDR reset pattern is inserted before the STOP of any emitted frame that includes a RSTACT CCC command

HDR Exit Pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. This is used to send only the header to test ownership of the bus when there is a suspicion of problem after controller-role hand-off (new controller didn’t assert its controller-role by accessing the previous one in less than Activity State time). The HDR Exit Pattern is sent even if the message header {S/Sr + 0x7E addr + W } is ACKed.

0 (B_0x0): HDR Exit Pattern is not sent after the message header (MTYPE[3:0]=0001)

1 (B_0x1): HDR Exit Pattern is sent after the message header (MTYPE[3:0]=0001) to generate an escalation fault

High-keeper enable on SDA line (when I3C is acting as a controller) This bit can be modified only when I3C_CFGR.EN=0.

0 (B_0x0): High-Keeper is disabled

1 (B_0x1): High-Keeper is enabled, and the weak pull-up is effective on the T bit, instead of the open-drain class pull-up.

Hot Join request acknowledge (when I3C is acting as a controller) After the NACK, the message continues as initially programmed (the hot-joining target is aware of the NACK and surely emits another hot-join request later on). After the ACK, the message continues as initially programmed. The software is aware by the HJ interrupt (flag I3C_EVR.HJF is set) and initiates the ENTDAA sequence later on, potentially preventing others Hot Join requests with a Disable target events command (DISEC, with DISHJ=1). Independently of the HJACK configuration, further Hot Join request(s) are NACKed until the Hot Join flag, HJF, is cleared. However, a NACKed target can be assigned a dynamic address by the ENTDAA sequence initiated later on by the first HJ request, preventing this target to emit an HJ request again.

0 (B_0x0): Hot Join request is NACKed

1 (B_0x1): Hot Join request is ACKed

RX-FIFO DMA request enable (whatever I3C is acting as controller/target)

• Software reads and pops a data byte/word from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register.
• A next data byte/word is to be read by the software either via polling on the flag I3C_EVR.RXFNEF=1 or via interrupt notification (enabled by I3C_IER.RXFNEIE=1).
• DMA reads and pops data byte(s)/word(s) from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register.
• A next data byte/word is automatically read by the programmed hardware (i.e. via the asserted RX-FIFO DMA request from the I3C and the programmed DMA channel).

0 (B_0x0): DMA mode is disabled for RX-FIFO

1 (B_0x1): DMA mode is enabled for RX-FIFO

RX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written.

0 (B_0x0): no action

1 (B_0x1): flush RX-FIFO

RX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the RX-FIFO level, when the I3C_EVR.RXFNEF flag is set (and consequently if RXDMAEN=1 when is asserted a DMA RX request). RXFNEF is set when 1 byte is to be read in RX-FIFO (i.e. in I3C_RDR). RXFNEF is set when 4 bytes are to be read in RX-FIFO (i.e. in I3C_RDWR).

0 (B_0x0): 1-byte threshold

1 (B_0x1): 4-byte threshold

TX-FIFO DMA request enable (whatever I3C is acting as controller/target)

• Software writes and pushes a data byte/word into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register, to be transmitted over the I3C bus.
• A next data byte/word is to be written by the software either via polling on the flag I3C_EVR.TXFNFF=1 or via interrupt notification (enabled by I3C_IER.TXFNFIE=1).
• DMA writes and pushes data byte(s)/word(s) into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register.
• A next data byte/word transfer is automatically pushed by the programmed hardware (i.e. via the asserted TX-FIFO DMA request from the I3C and the programmed DMA channel).

0 (B_0x0): DMA mode is disabled for TX-FIFO

1 (B_0x1): DMA mode is enabled for TX-FIFO

TX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written. When the I3C is acting as target, this bit can be used to flush the TX-FIFO on a private read if the controller has early ended the read data (i.e. driven low the T bit) and there is/are remaining data in the TX-FIFO (i.e. I3C_SR.ABT=1 and I3C_SR.XDCNT[15:0] I3C_TGTTDR.TGTTDCNT[15:0]).

0 (B_0x0): no action

1 (B_0x1): flush TX-FIFO

TX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the TX-FIFO level, when the I3C_EVR.TXFNFF flag is set (and consequently if TXDMAEN=1 when is asserted a DMA TX request). TXFNFF is set when 1 byte is to be written in TX-FIFO (i.e. in I3C_TDR). TXFNFF is set when 4 bytes are to be written in TX-FIFO (i.e. in I3C_TDWR).

0 (B_0x0): 1-byte threshold

1 (B_0x1): 4-byte threshold

S-FIFO DMA request enable (when I3C is acting as controller) Condition: When RMODE=1 (FIFO is enabled for the status):

• Software reads and pops a status word from S-FIFO i.e. reads I3C_SR register after a completed frame (I3C_EVR.FCF=1) or an error (I3C_EVR.ERRF=1).
• A status word can be read by the software either via polling on these register flags or via interrupt notification (enabled by I3C_IER.FCIE=1 and I3C_IER.ERRIE=1).
• DMA reads and pops status word(s) from S-FIFO i.e. reads I3C_SR register.
• Status word(s) are automatically read by the programmed hardware (i.e. via the asserted S-FIFO DMA request from the I3C and the programmed DMA channel).

0 (B_0x0): DMA mode is disabled for S-FIFO

1 (B_0x1): DMA mode is enabled for S-FIFO

S-FIFO flush (when I3C is acting as controller) When I3C is acting as I3C controller, this bit can only be written (and is only used when I3C is acting as controller).

0 (B_0x0): no action

1 (B_0x1): flush S-FIFO

S-FIFO enable / status receive mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the enabling the FIFO for the status (S-FIFO) vs the received status from the target on the I3C bus. When I3C is acting as target, this bit must be cleared.

• Status register (i.e. I3C_SR) is used without FIFO mechanism.
• There is no SCL stretch if a new status register content is not read.
• Status register must be read before being lost/overwritten. All message status must be read. There is SCL stretch when there is no more space in the S-FIFO.

0 (B_0x0): S-FIFO is disabled, and the

1 (B_0x1): S-FIFO is enabled.

transmit mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the C-FIFO and TX-FIFO management vs the emitted frame on the I3C bus. A frame transfer starts as soon as first control word is present in C-FIFO.

0 (B_0x0): C-FIFO and TX-FIFO are not preloaded before starting to emit a frame transfer.

1 (B_0x1): C-FIFO and TX-FIFO are first preloaded (also TX-FIFO if needed (depending on the frame format) before starting to emit a frame transfer.

C-FIFO DMA request enable (when I3C is acting as controller) When I3C is acting as controller:

• Software writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame.
• A next control word transfer can be written by software either via polling on the flag I3C_EVR.CFNFF=1 or via interrupt notification (enabled by I3C_IER.CFNFIE=1).
• DMA writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame.
• A next control word transfer is automatically written by the programmed hardware (i.e. via the asserted C-FIFO DMA request from the I3C and the programmed DMA channel).

0 (B_0x0): DMA mode is disabled for C-FIFO

1 (B_0x1): DMA mode is enabled for C-FIFO

C-FIFO flush (when I3C is acting as controller) This bit can only be written.

0 (B_0x0): no action

1 (B_0x1): flush C-FIFO

frame transfer set (a.k.a. software trigger) (when I3C is acting as controller) This bit can only be written. When I3C is acting as I3C controller: Note: If this bit is not set, the other alternative for the software to initiate a frame transfer is to directly write the first control word register (i.e. I3C_CR) while C-FIFO is empty (i.e. I3C_EVR.CFEF=1). Then, if the first written control word is not tagged as a message end (i.e I3C_CR.MEND=0), it causes the hardware to assert the flag I3C_EVR.CFNFF (C-FIFO not full and a next control word is needed).

0 (B_0x0): no action

1 (B_0x1): setting this bit initiates a frame transfer by causing the hardware to assert the flag I3C_EVR.CFNFF (C-FIFO not full and a control word is needed)