MISSMEN=B_0x0, WAYSEL=B_0x0, CACHEINV=B_0x0, HITMRST=B_0x0, HITMEN=B_0x0, EN=B_0x0, MISSMRST=B_0x0
ICACHE control register
| EN | enable 0 (B_0x0): cache disabled 1 (B_0x1): cache enabled |
| CACHEINV | cache invalidation Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. 0 (B_0x0): no effect 1 (B_0x1): invalidate entire cache (all cache lines valid bit = 0) |
| WAYSEL | cache associativity mode selection This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). 0 (B_0x0): direct mapped cache (1-way cache) 1 (B_0x1): n-way set associative cache (reset value) |
| HITMEN | hit monitor enable 0 (B_0x0): cache hit monitor switched off. Stopping the monitor does not reset it. 1 (B_0x1): cache hit monitor enabled |
| MISSMEN | miss monitor enable 0 (B_0x0): cache miss monitor switched off. Stopping the monitor does not reset it. 1 (B_0x1): cache miss monitor enabled |
| HITMRST | hit monitor reset 0 (B_0x0): no effect 1 (B_0x1): reset cache hit monitor |
| MISSMRST | miss monitor reset 0 (B_0x0): no effect 1 (B_0x1): reset cache miss monitor |