stm32 /stm32h5 /STM32H503 /RCC /RCC_CFGR2

AHB prescaler Set and reset by software to control the division factor of rcc_hclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks 0xxx: rcc_hclk = sys_ck (default after reset)

8 (B_0x8): rcc_hclk = sys_ck / 2

9 (B_0x9): rcc_hclk = sys_ck / 4

10 (B_0xA): rcc_hclk = sys_ck / 8

11 (B_0xB): rcc_hclk = sys_ck / 16

12 (B_0xC): rcc_hclk = sys_ck / 64

13 (B_0xD): rcc_hclk = sys_ck / 128

14 (B_0xE): rcc_hclk = sys_ck / 256

15 (B_0xF): rcc_hclk = sys_ck / 512

APB low-speed prescaler (APB1) Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)

4 (B_0x4): rcc_pclk1 = rcc_hclk1 / 2

5 (B_0x5): rcc_pclk1 = rcc_hclk1 / 4

6 (B_0x6): rcc_pclk1 = rcc_hclk1 / 8

7 (B_0x7): rcc_pclk1 = rcc_hclk1 / 16

APB high-speed prescaler (APB2) Set and reset by software to control APB high-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1

4 (B_0x4): rcc_pclk2 = rcc_hclk1 / 2

5 (B_0x5): rcc_pclk2 = rcc_hclk1 / 4

6 (B_0x6): rcc_pclk2 = rcc_hclk1 / 8

7 (B_0x7): rcc_pclk2 = rcc_hclk1 / 16

APB low-speed prescaler (APB3) Set and reset by software to control APB low-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write. 0xx: rcc_pclk3 = rcc_hclk1

4 (B_0x4): rcc_pclk3 = rcc_hclk1 / 2

5 (B_0x5): rcc_pclk3 = rcc_hclk1 / 4

6 (B_0x6): rcc_pclk3 = rcc_hclk1 / 8

7 (B_0x7): rcc_pclk3 = rcc_hclk1 / 16

AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals from RCC_AHB1ENR are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from RCC_AHB1ENR are off. enable control bits

0 (B_0x0): AHB1 clock enabled, distributed to peripherals according to their dedicated clock

1 (B_0x1): AHB1 clock disabled

AHB2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR are used and when their clocks are disabled in RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR are off. enable control bits

0 (B_0x0): AHB2 clock enabled, distributed to peripherals according to their dedicated clock

1 (B_0x1): AHB2 clock disabled

AHB4 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB4 peripherals from RCC_AHB4ENR are used and when their clocks are disabled in RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from RCC_AHB4ENR are off. enable control bits

0 (B_0x0): AHB4 clock enabled, distributed to peripherals according to their dedicated clock

1 (B_0x1): AHB4 clock disabled

APB1 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. control bits

0 (B_0x0): APB1 clock enabled, distributed to peripherals according to their dedicated clock enable

1 (B_0x1): APB1 clock disabled

APB2 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. control bits

0 (B_0x0): APB2 clock enabled, distributed to peripherals according to their dedicated clock enable

1 (B_0x1): APB2 clock disabled

APB3 clock disable value.Set and cleared by software This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. control bits

0 (B_0x0): APB3 clock enabled, distributed to peripherals according to their dedicated clock enable

1 (B_0x1): APB3 clock disabled