CCLKEN=B_0x0, WREN=B_0x0, FACCEN=B_0x0, CPSIZE=B_0x0, WAITCFG=B_0x0, FMCEN=B_0x0, BURSTEN=B_0x0, EXTMOD=B_0x0, WAITPOL=B_0x0, CBURSTRW=B_0x0, WAITEN=B_0x0, MWID=B_0x0, MBKEN=B_0x0, ASYNCWAIT=B_0x0, MUXEN=B_0x0, WFDIS=B_0x0, MTYP=B_0x0, NBLSET=B_0x0
SRAM/NOR-flash chip-select control register for bank 3
| MBKEN | Memory bank enable bit 0 (B_0x0): Corresponding memory bank is disabled. 1 (B_0x1): Corresponding memory bank is enabled. |
| MUXEN | Address/data multiplexing enable bit 0 (B_0x0): Address/data non multiplexed 1 (B_0x1): Address/data multiplexed on databus (default after reset) |
| MTYP | Memory type 0 (B_0x0): SRAM/FRAM (default after reset for Bank 2. 1 (B_0x1): PSRAM (CRAM) / FRAM 2 (B_0x2): NOR flash/OneNAND flash (default after reset for Bank 1) |
| MWID | Memory data bus width 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits (default after reset) |
| FACCEN | Flash access enable 0 (B_0x0): Corresponding NOR flash memory access is disabled. 1 (B_0x1): Corresponding NOR flash memory access is enabled (default after reset). |
| BURSTEN | Burst enable bit 0 (B_0x0): Burst mode disabled (default after reset). 1 (B_0x1): Burst mode enable. |
| WAITPOL | Wait signal polarity bit 0 (B_0x0): NWAIT active low (default after reset) 1 (B_0x1): NWAIT active high |
| WAITCFG | Wait timing configuration 0 (B_0x0): NWAIT signal is active one data cycle before wait state (default after reset). 1 (B_0x1): NWAIT signal is active during wait state (not used for PSRAM). |
| WREN | Write enable bit 0 (B_0x0): Write operations are disabled in the bank by the FMC, an AHB error is reported. 1 (B_0x1): Write operations are enabled for the bank by the FMC (default after reset). |
| WAITEN | Wait enable bit 0 (B_0x0): NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period). 1 (B_0x1): NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset). |
| EXTMOD | Extended mode enable 0 (B_0x0): values inside FMC_BWTR register are not taken into account (default after reset) 1 (B_0x1): values inside FMC_BWTR register are taken into account |
| ASYNCWAIT | Wait signal during asynchronous transfers 0 (B_0x0): NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset). 1 (B_0x1): NWAIT signal is taken in to account when running an asynchronous protocol. |
| CPSIZE | CRAM page size 0 (B_0x0): No burst split when crossing page boundary (default after reset) 1 (B_0x1): 128 bytes 2 (B_0x2): 256 bytes 3 (B_0x3): 512 bytes 4 (B_0x4): 1024 bytes |
| CBURSTRW | Write burst enable 0 (B_0x0): Write operations are always performed in Asynchronous mode. 1 (B_0x1): Write operations are performed in Synchronous mode. |
| CCLKEN | Continuous clock enable 0 (B_0x0): The FMC_CLK is only generated during the synchronous memory access (read/write transaction). 1 (B_0x1): The FMC_CLK is generated continuously during asynchronous and synchronous access. |
| WFDIS | Write FIFO disable 0 (B_0x0): Write FIFO enabled (Default after reset) 1 (B_0x1): Write FIFO disabled |
| NBLSET | Byte lane (NBL) setup 0 (B_0x0): NBL setup time is 0 AHB clock cycle 1 (B_0x1): NBL setup time is 1 AHB clock cycle 2 (B_0x2): NBL setup time is 2 AHB clock cycles 3 (B_0x3): NBL setup time is 3 AHB clock cycles |
| FMCEN | FMC controller enable 0 (B_0x0): Disable the FMC controller 1 (B_0x1): Enable the FMC controller |