stm32 /stm32h5 /STM32H533 /ADC /ADC_CFGR

Direct memory access enable

0 (B_0x0): DMA disabled

1 (B_0x1): DMA enabled

Direct memory access configuration

0 (B_0x0): DMA One Shot mode selected

1 (B_0x1): DMA Circular mode selected

Data resolution

0 (B_0x0): 12-bit

1 (B_0x1): 10-bit

2 (B_0x2): 8-bit

3 (B_0x3): 6-bit

External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: … Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): adc_ext_trg0

1 (B_0x1): adc_ext_trg1

2 (B_0x2): adc_ext_trg2

3 (B_0x3): adc_ext_trg3

4 (B_0x4): adc_ext_trg4

5 (B_0x5): adc_ext_trg5

6 (B_0x6): adc_ext_trg6

7 (B_0x7): adc_ext_trg7

8 (B_0x8): adc_ext_trg8

9 (B_0x9): adc_ext_trg9

10 (B_0xA): adc_ext_trg10

11 (B_0xB): adc_ext_trg11

12 (B_0xC): adc_ext_trg12

13 (B_0xD): adc_ext_trg13

14 (B_0xE): adc_ext_trg14

15 (B_0xF): adc_ext_trg15

16 (B_0x10): adc_ext_trg16

17 (B_0x11): adc_ext_trg17

18 (B_0x12): adc_ext_trg18

19 (B_0x13): adc_ext_trg19

20 (B_0x14): adc_ext_trg20

21 (B_0x15): adc_ext_trg21

22 (B_0x16): adc_ext_trg22

23 (B_0x17): adc_ext_trg23

24 (B_0x18): adc_ext_trg24

25 (B_0x19): adc_ext_trg25

26 (B_0x1A): adc_ext_trg26

27 (B_0x1B): adc_ext_trg27

28 (B_0x1C): adc_ext_trg28

29 (B_0x1D): adc_ext_trg29

30 (B_0x1E): adc_ext_trg30

31 (B_0x1F): adc_ext_trg31

External trigger enable and polarity selection for regular channels

0 (B_0x0): Hardware trigger detection disabled (conversions can be launched by software)

1 (B_0x1): Hardware trigger detection on the rising edge

2 (B_0x2): Hardware trigger detection on the falling edge

3 (B_0x3): Hardware trigger detection on both the rising and falling edges

Overrun mode

0 (B_0x0): ADC_DR register is preserved with the old data when an overrun is detected.

1 (B_0x1): ADC_DR register is overwritten with the last conversion result when an overrun is detected.

Single / continuous conversion mode for regular conversions

0 (B_0x0): Single conversion mode

1 (B_0x1): Continuous conversion mode

Delayed conversion mode

0 (B_0x0): Auto-delayed conversion mode off

1 (B_0x1): Auto-delayed conversion mode on

Data alignment

0 (B_0x0): Right alignment

1 (B_0x1): Left alignment

Discontinuous mode for regular channels

0 (B_0x0): Discontinuous mode for regular channels disabled

1 (B_0x1): Discontinuous mode for regular channels enabled

Discontinuous mode channel count

0 (B_0x0): 1 channel

1 (B_0x1): 2 channels

7 (B_0x7): 8 channels

Discontinuous mode on injected channels

0 (B_0x0): Discontinuous mode on injected channels disabled

1 (B_0x1): Discontinuous mode on injected channels enabled

JSQR queue mode

0 (B_0x0): JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR.

1 (B_0x1): JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence.

Enable the watchdog 1 on a single channel or on all channels

0 (B_0x0): Analog watchdog 1 enabled on all channels

1 (B_0x1): Analog watchdog 1 enabled on a single channel

Analog watchdog 1 enable on regular channels

0 (B_0x0): Analog watchdog 1 disabled on regular channels

1 (B_0x1): Analog watchdog 1 enabled on regular channels

Analog watchdog 1 enable on injected channels

0 (B_0x0): Analog watchdog 1 disabled on injected channels

1 (B_0x1): Analog watchdog 1 enabled on injected channels

Automatic injected group conversion

0 (B_0x0): Automatic injected group conversion disabled

1 (B_0x1): Automatic injected group conversion enabled

Analog watchdog 1 channel selection

0 (B_0x0): ADC analog input channel 0 monitored by AWD1 (available on ADC1 only)

1 (B_0x1): ADC analog input channel 1 monitored by AWD1

19 (B_0x13): ADC analog input channel 19 monitored by AWD1

Injected queue disable

0 (B_0x0): Injected queue enabled

1 (B_0x1): Injected queue disabled