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stm32 /stm32h5 /STM32H533 /ADC /ADC_OFR2

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Interpret as ADC_OFR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0OFFSET0 (B_0x0)OFFSETPOS 0 (B_0x0)SATEN 0OFFSET_CH0 (OFFSET_EN)OFFSET_EN

SATEN=B_0x0, OFFSETPOS=B_0x0

Description

ADC offset 2 register

Fields

OFFSET

Data offset y for the channel programmed into bits OFFSET_CH[4:0]
OFFSETPOS

Positive offset

0 (B_0x0): Negative offset

1 (B_0x1): Positive offset
SATEN

Saturation enable

0 (B_0x0): No saturation control, offset result can be signed

1 (B_0x1): Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF
OFFSET_CH

Channel selection for the data offset y
OFFSET_EN

Offset y enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32