stm32 /stm32h5 /STM32H533 /CRS /CRS_CR

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Interpret as CRS_CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SYNCOKIE 0 (B_0x0)SYNCWARNIE 0 (B_0x0)ERRIE 0 (B_0x0)ESYNCIE 0 (B_0x0)CEN 0 (B_0x0)AUTOTRIMEN 0 (B_0x0)SWSYNC 0TRIM

ESYNCIE=B_0x0, SWSYNC=B_0x0, AUTOTRIMEN=B_0x0, CEN=B_0x0, SYNCWARNIE=B_0x0, SYNCOKIE=B_0x0, ERRIE=B_0x0

Description

CRS control register

Fields

SYNCOKIE

SYNC event OK interrupt enable

0 (B_0x0): SYNC event OK (SYNCOKF) interrupt disabled

1 (B_0x1): SYNC event OK (SYNCOKF) interrupt enabled

SYNCWARNIE

SYNC warning interrupt enable

0 (B_0x0): SYNC warning (SYNCWARNF) interrupt disabled

1 (B_0x1): SYNC warning (SYNCWARNF) interrupt enabled

ERRIE

Synchronization or trimming error interrupt enable

0 (B_0x0): Synchronization or trimming error (ERRF) interrupt disabled

1 (B_0x1): Synchronization or trimming error (ERRF) interrupt enabled

ESYNCIE

Expected SYNC interrupt enable

0 (B_0x0): Expected SYNC (ESYNCF) interrupt disabled

1 (B_0x1): Expected SYNC (ESYNCF) interrupt enabled

CEN

Frequency error counter enable

0 (B_0x0): Frequency error counter disabled

1 (B_0x1): Frequency error counter enabled

AUTOTRIMEN

Automatic trimming enable

0 (B_0x0): Automatic trimming disabled, TRIM bits can be adjusted by the user.

1 (B_0x1): Automatic trimming enabled, TRIM bits are read-only and under hardware control.

SWSYNC

Generate software SYNC event

0 (B_0x0): No action

1 (B_0x1): A software SYNC event is generated.

TRIM

HSI48 oscillator smooth trimming

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