stm32 /stm32h5 /STM32H533 /DAC /DAC_SR

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Interpret as DAC_SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DAC1RDY 0 (B_0x0)DORSTAT1 0 (B_0x0)DMAUDR1 0 (B_0x0)CAL_FLAG1 0 (B_0x0)BWST1 0 (B_0x0)DAC2RDY 0 (B_0x0)DORSTAT2 0 (B_0x0)DMAUDR2 0 (B_0x0)CAL_FLAG2 0 (B_0x0)BWST2

DMAUDR2=B_0x0, CAL_FLAG1=B_0x0, DAC1RDY=B_0x0, CAL_FLAG2=B_0x0, DORSTAT2=B_0x0, BWST1=B_0x0, DAC2RDY=B_0x0, BWST2=B_0x0, DORSTAT1=B_0x0, DMAUDR1=B_0x0

Description

DAC status register

Fields

DAC1RDY

DAC channel1 ready status bit

0 (B_0x0): DAC channel1 is not yet ready to accept the trigger nor output data

1 (B_0x1): DAC channel1 is ready to accept the trigger or output data

DORSTAT1

DAC channel1 output register status bit

0 (B_0x0): DOR[11:0] is used actual DAC output

1 (B_0x1): DORB[11:0] is used actual DAC output

DMAUDR1

DAC channel1 DMA underrun flag

0 (B_0x0): No DMA underrun error condition occurred for DAC channel1

1 (B_0x1): DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG1

DAC channel1 calibration offset status

0 (B_0x0): calibration trimming value is lower than the offset correction value

1 (B_0x1): calibration trimming value is equal or greater than the offset correction value

BWST1

DAC channel1 busy writing sample time flag

0 (B_0x0): There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written

1 (B_0x1): There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DAC2RDY

DAC channel2 ready status bit

0 (B_0x0): DAC channel2 is not yet ready to accept the trigger nor output data

1 (B_0x1): DAC channel2 is ready to accept the trigger or output data

DORSTAT2

DAC channel2 output register status bit

0 (B_0x0): DOR[11:0] is used actual DAC output

1 (B_0x1): DORB[11:0] is used actual DAC output

DMAUDR2

DAC channel2 DMA underrun flag

0 (B_0x0): No DMA underrun error condition occurred for DAC channel2

1 (B_0x1): DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate).

CAL_FLAG2

DAC channel2 calibration offset status

0 (B_0x0): calibration trimming value is lower than the offset correction value

1 (B_0x1): calibration trimming value is equal or greater than the offset correction value

BWST2

DAC channel2 busy writing sample time flag

0 (B_0x0): There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written

1 (B_0x1): There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written

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