stm32 /stm32h5 /STM32H533 /DLYBOS1 /DLYB_CFGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DLYB_CFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SEL0UNIT0LNG0 (B_0x0)LNGF

LNGF=B_0x0

Description

DLYB configuration register

Fields

SEL

Phase for the output clock.

UNIT

Delay of a unit delay cell.

LNG

Delay line length value

LNGF

Length valid flag

0 (B_0x0): Length value in LNG is not valid.

1 (B_0x1): Length value in LNG is valid.

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