stm32 /stm32h5 /STM32H533 /FDCAN /FDCAN_PSR

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Interpret as FDCAN_PSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LEC0 (B_0x0)ACT0 (B_0x0)EP 0 (B_0x0)EW 0 (B_0x0)BO 0DLEC0 (B_0x0)RESI 0 (B_0x0)RBRS 0 (B_0x0)REDL 0 (B_0x0)PXE 0TDCV

BO=B_0x0, RBRS=B_0x0, EP=B_0x0, EW=B_0x0, PXE=B_0x0, REDL=B_0x0, RESI=B_0x0, ACT=B_0x0, LEC=B_0x0

Description

FDCAN protocol status register

Fields

LEC

Last error code

0 (B_0x0): No Error: No error occurred since LEC has been reset by successful reception or transmission.

1 (B_0x1): Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.

2 (B_0x2): Form Error: A fixed format part of a received frame has the wrong format.

3 (B_0x3): AckError: The message transmitted by the FDCAN was not acknowledged by another node.

4 (B_0x4): Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant.

5 (B_0x5): Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive.

6 (B_0x6): CRCError: The CRC check sum of a received message was incorrect.

7 (B_0x7): NoChange: Any read access to the Protocol status register re-initializes the LEC to 7’.

ACT

Activity

0 (B_0x0): Synchronizing: node is synchronizing on CAN communication.

1 (B_0x1): Idle: node is neither receiver nor transmitter.

2 (B_0x2): Receiver: node is operating as receiver.

3 (B_0x3): Transmitter: node is operating as transmitter.

EP

Error passive

0 (B_0x0): The FDCAN is in the Error_Active state.

1 (B_0x1): The FDCAN is in the Error_Passive state.

EW

Warning Sstatus

0 (B_0x0): Both error counters are below the Error_Warning limit of 96.

1 (B_0x1): At least one of error counter has reached the Error_Warning limit of 96.

BO

Bus_Off status

0 (B_0x0): The FDCAN is not Bus_Off.

1 (B_0x1): The FDCAN is in Bus_Off state.

DLEC

Data last error code

RESI

ESI flag of last received FDCAN message

0 (B_0x0): Last received FDCAN message did not have its ESI flag set.

1 (B_0x1): Last received FDCAN message had its ESI flag set.

RBRS

BRS flag of last received FDCAN message

0 (B_0x0): Last received FDCAN message did not have its BRS flag set.

1 (B_0x1): Last received FDCAN message had its BRS flag set.

REDL

Received FDCAN message

0 (B_0x0): Since this bit was reset by the CPU, no FDCAN message has been received.

1 (B_0x1): Message in FDCAN format with EDL flag set has been received.

PXE

Protocol exception event

0 (B_0x0): No protocol exception event occurred since last read access

1 (B_0x1): Protocol exception event occurred

TDCV

Transmitter delay compensation value

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