ATTHIZ=B_0x0, ATTSET=B_0x0
Attribute memory space timing register
| ATTSET | Attribute memory setup time 0 (B_0x0): 1 HCLK cycle 254 (B_0xFE): 255 HCLK cycles |
| ATTWAIT | Attribute memory wait time 1 (B_0x1): 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) 254 (B_0xFE): 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) |
| ATTHOLD | Attribute memory hold time 1 (B_0x1): 1 HCLK cycle for write access / 3 HCLK cycles for read access 254 (B_0xFE): 254 HCLK cycles for write access / 256 HCLK cycles for read access |
| ATTHIZ | Attribute memory data bus Hi-Z time 0 (B_0x0): 0 HCLK cycle 254 (B_0xFE): 255 HCLK cycles |