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stm32 /stm32h5 /STM32H533 /FMC /FMC_PCSCNTR

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Interpret as FMC_PCSCNTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CSCOUNT0 (B_0x0)CNTB1EN 0 (B_0x0)CNTB2EN 0 (B_0x0)CNTB3EN 0 (B_0x0)CNTB4EN

CNTB2EN=B_0x0, CNTB1EN=B_0x0, CNTB4EN=B_0x0, CNTB3EN=B_0x0

Description

PSRAM chip select counter register

Fields

CSCOUNT

Chip select counter.
CNTB1EN

Counter Bank 1 enable

0 (B_0x0): Counter disabled for Bank 1

1 (B_0x1): Counter enabled for Bank 1
CNTB2EN

Counter Bank 2 enable

0 (B_0x0): Counter disabled for Bank 2

1 (B_0x1): Counter enabled for Bank 2
CNTB3EN

Counter Bank 3 enable

0 (B_0x0): Counter disabled for Bank 3.

1 (B_0x1): Counter enabled for Bank 3
CNTB4EN

Counter Bank 4 enable

0 (B_0x0): Counter disabled for Bank 4

1 (B_0x1): Counter enabled for Bank 4

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32