MEMHIZ=B_0x0, MEMSET=B_0x0
Common memory space timing register
| MEMSET | Common memory x setup time 0 (B_0x0): 1 HCLK cycle 254 (B_0xFE): 255 HCLK cycles |
| MEMWAIT | Common memory wait time 1 (B_0x1): 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT) 254 (B_0xFE): 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) |
| MEMHOLD | Common memory hold time 1 (B_0x1): 1 HCLK cycle for write access / 3 HCLK cycles for read access 254 (B_0xFE): 254 HCLK cycles for write access / 256 HCLK cycles for read access |
| MEMHIZ | Common memory x data bus Hi-Z time 0 (B_0x0): 1 HCLK cycle 254 (B_0xFE): 255 HCLK cycles |