MWID=B_0x0, NR=B_0x0, RBURST=B_0x0, SDCLK=B_0x0, RPIPE=B_0x0, NB=B_0x0, WP=B_0x0, NC=B_0x0
SDRAM control registers 1,2
| NC | Number of column address bits 0 (B_0x0): 8 bits 1 (B_0x1): 9 bits 2 (B_0x2): 10 bits 3 (B_0x3): 11 bits. |
| NR | Number of row address bits 0 (B_0x0): 11 bit 1 (B_0x1): 12 bits 2 (B_0x2): 13 bits |
| MWID | Memory data bus width. 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits |
| NB | Number of internal banks 0 (B_0x0): Two internal Banks 1 (B_0x1): Four internal Banks |
| CAS | CAS Latency 1 (B_0x1): 1 cycle 2 (B_0x2): 2 cycles 3 (B_0x3): 3 cycles |
| WP | Write protection 0 (B_0x0): Write accesses allowed 1 (B_0x1): Write accesses ignored |
| SDCLK | SDRAM clock configuration 0 (B_0x0): SDCLK clock disabled 1 (B_0x1): SDCLK period = 1x HCLK periods 2 (B_0x2): SDCLK period = 2 x HCLK periods 3 (B_0x3): SDCLK period = 3 x HCLK periods |
| RBURST | Burst read 0 (B_0x0): single read requests are not managed as bursts 1 (B_0x1): single read requests are always managed as bursts |
| RPIPE | Read pipe 0 (B_0x0): No clock cycle delay 1 (B_0x1): One clock cycle delay 2 (B_0x2): Two clock cycle delay |