TXSR=B_0x0, TRCD=B_0x0, TRAS=B_0x0, TMRD=B_0x0, TRP=B_0x0, TWR=B_0x0, TRC=B_0x0
SDRAM timing registers 1,2
| TMRD | Load Mode Register to Active 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TXSR | Exit Self-refresh delay 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TRAS | Self refresh time 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TRC | Row cycle delay 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TWR | Recovery delay 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TRP | Row precharge delay 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TRCD | Row to column delay 0 (B_0x0): 1 cycle. 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |