stm32 /stm32h5 /STM32H533 /GPDMA /GPDMA_C7BR1

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Interpret as GPDMA_C7BR1

BRSDEC=B_0x0, SDEC=B_0x0, BRDDEC=B_0x0, DDEC=B_0x0

Description

GPDMA channel 7 alternate block register 1

Fields

BNDT	block number of data bytes to transfer from the source
BRC	Block repeat counter
SDEC	source address decrement 0 (B_0x0): At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3. 1 (B_0x1): At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.
DDEC	destination address decrement 0 (B_0x0): At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3. 1 (B_0x1): At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.
BRSDEC	Block repeat source address decrement 0 (B_0x0): at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2. 1 (B_0x1): at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.
BRDDEC	Block repeat destination address decrement 0 (B_0x0): at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2. 1 (B_0x1): at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.

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