stm32 /stm32h5 /STM32H533 /GTZC1_TZSC /GTZC1_TZSC_SECCFGR2

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Interpret as GTZC1_TZSC_SECCFGR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)FDCAN1SEC 0 (B_0x0)FDCAN2SEC 0 (B_0x0)UCPDSEC 0 (B_0x0)TIM1SEC 0 (B_0x0)SPI1SEC 0 (B_0x0)TIM8SEC 0 (B_0x0)USART1SEC 0 (B_0x0)TIM15SEC 0 (B_0x0)SPI4SEC 0 (B_0x0)SPI6SEC 0 (B_0x0)SAI1SEC 0 (B_0x0)SAI2SEC 0 (B_0x0)USBSEC 0 (B_0x0)LPUART1SEC 0 (B_0x0)I2C3SEC 0 (B_0x0)LPTIM1SEC 0 (B_0x0)LPTIM3SEC 0 (B_0x0)LPTIM4SEC 0 (B_0x0)LPTIM5SEC

LPTIM5SEC=B_0x0, LPTIM3SEC=B_0x0, I2C3SEC=B_0x0, SPI6SEC=B_0x0, FDCAN2SEC=B_0x0, LPTIM4SEC=B_0x0, LPUART1SEC=B_0x0, TIM15SEC=B_0x0, SPI1SEC=B_0x0, SAI1SEC=B_0x0, USART1SEC=B_0x0, SPI4SEC=B_0x0, FDCAN1SEC=B_0x0, LPTIM1SEC=B_0x0, SAI2SEC=B_0x0, USBSEC=B_0x0, TIM1SEC=B_0x0, TIM8SEC=B_0x0, UCPDSEC=B_0x0

Description

GTZC1 TZSC secure configuration register 2

Fields

FDCAN1SEC

secure access mode for FDCAN1

0 (B_0x0): non-secure

1 (B_0x1): secure

FDCAN2SEC

secure access mode for FDCAN2

0 (B_0x0): non-secure

1 (B_0x1): secure

UCPDSEC

secure access mode for UCPD

0 (B_0x0): non-secure

1 (B_0x1): secure

TIM1SEC

secure access mode for TIM1

0 (B_0x0): non-secure

1 (B_0x1): secure

SPI1SEC

secure access mode for SPI1

0 (B_0x0): non-secure

1 (B_0x1): secure

TIM8SEC

secure access mode for TIM8

0 (B_0x0): non-secure

1 (B_0x1): secure

USART1SEC

secure access mode for USART1

0 (B_0x0): non-secure

1 (B_0x1): secure

TIM15SEC

secure access mode for TIM15

0 (B_0x0): non-secure

1 (B_0x1): secure

SPI4SEC

secure access mode for SPI4

0 (B_0x0): non-secure

1 (B_0x1): secure

SPI6SEC

secure access mode for SPI6

0 (B_0x0): non-secure

1 (B_0x1): secure

SAI1SEC

secure access mode for SAI1

0 (B_0x0): non-secure

1 (B_0x1): secure

SAI2SEC

secure access mode for SAI2

0 (B_0x0): non-secure

1 (B_0x1): secure

USBSEC

secure access mode for USB

0 (B_0x0): non-secure

1 (B_0x1): secure

LPUART1SEC

secure access mode for LPUART

0 (B_0x0): non-secure

1 (B_0x1): secure

I2C3SEC

secure access mode for I2C3

0 (B_0x0): non-secure

1 (B_0x1): secure

LPTIM1SEC

secure access mode for LPTIM1

0 (B_0x0): non-secure

1 (B_0x1): secure

LPTIM3SEC

secure access mode for LPTIM3

0 (B_0x0): non-secure

1 (B_0x1): secure

LPTIM4SEC

secure access mode for LPTIM4

0 (B_0x0): non-secure

1 (B_0x1): secure

LPTIM5SEC

secure access mode for LPTIM5

0 (B_0x0): non-secure

1 (B_0x1): secure

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