stm32 /stm32h5 /STM32H533 /HASH /HASH_SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HASH_SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DINIS 0 (B_0x0)DCIS 0 (B_0x0)DMAS 0 (B_0x0)BUSY 0NBWP0 (B_0x0)DINNE 0NBWE

DINIS=B_0x0, DCIS=B_0x0, DINNE=B_0x0, BUSY=B_0x0, DMAS=B_0x0

Description

HASH status register

Fields

DINIS

Data input interrupt status

0 (B_0x0): Less than 16 locations are free in the input buffer

1 (B_0x1): A new block can be entered into the input buffer.

DCIS

Digest calculation completion interrupt status

0 (B_0x0): No digest available in the HASH_HRx registers (zeros are returned)

1 (B_0x1): Digest calculation complete, a digest is available in the HASH_HRx registers.

DMAS

DMA Status

0 (B_0x0): DMA interface is disabled (DMAE = 0) and no transfer is ongoing

1 (B_0x1): DMA interface is enabled (DMAE = 1) or a transfer is ongoing

BUSY

Busy bit

0 (B_0x0): No block is currently being processed

1 (B_0x1): The hash core is processing a block of data

NBWP

Number of words already pushed

DINNE

DIN not empty

0 (B_0x0): No data are present in the data input buffer

1 (B_0x1): The input buffer contains at least one word of data

NBWE

Number of words expected

Links

()