SDMAEN=B_0x0, TMODE=B_0x0, RSTPTRN=B_0x0, RXTHRES=B_0x0, TSFSET=B_0x0, RXFLUSH=B_0x0, RXDMAEN=B_0x0, HKSDAEN=B_0x0, TXTHRES=B_0x0, NOARBH=B_0x0, CFLUSH=B_0x0, SMODE=B_0x0, SFLUSH=B_0x0, EN=B_0x0, TXDMAEN=B_0x0, EXITPTRN=B_0x0, TXFLUSH=B_0x0, CDMAEN=B_0x0, HJACK=B_0x0, CRINIT=B_0x0
I3C configuration register
| EN | I3C enable (whatever I3C acts as controller/target) 0 (B_0x0): I3C is disabled 1 (B_0x1): I3C is enabled |
| CRINIT | Initial controller/target role 0 (B_0x0): target role 1 (B_0x1): controller role |
| NOARBH | No arbitrable header after a start (when I3C acts as a controller) 0 (B_0x0): An arbitrable header (0b111_1110 + RnW = 0) is emitted after a start and before a legacy Iless thansup>2less than/sup>C message or an I3C SDR private read/write message (default). 1 (B_0x1): No arbitrable header |
| RSTPTRN | HDR reset pattern enable (when I3C acts as a controller) 0 (B_0x0): standard stop emitted at the end of a frame 1 (B_0x1): HDR reset pattern is inserted before the stop of any emitted frame that includes a RSTACT CCC command |
| EXITPTRN | HDR exit pattern enable (when I3C acts as a controller) 0 (B_0x0): HDR exit pattern is not sent after the issued message header (MTYPE[3:0] = 0001 in the I3C_CR register). 1 (B_0x1): HDR exit pattern is sent after the issued message header (MTYPE[3:0] = 0001). |
| HKSDAEN | High-keeper enable on SDA line (when I3C acts as a controller) 0 (B_0x0): High-keeper is disabled 1 (B_0x1): High-keeper is enabled, and the weak pull-up is effective on the T bit, instead of the open-drain class pull-up. |
| HJACK | Hot-join request acknowledge (when I3C acts as a controller) 0 (B_0x0): hot-join request is not acknowledged 1 (B_0x1): hot-join request is acknowledged |
| RXDMAEN | RX-FIFO DMA request enable (whatever I3C acts as controller/target) 0 (B_0x0): DMA mode is disabled for RX-FIFO 1 (B_0x1): DMA mode is enabled for RX-FIFO |
| RXFLUSH | RX-FIFO flush (whatever I3C acts as controller/target) 0 (B_0x0): no action 1 (B_0x1): flush RX-FIFO |
| RXTHRES | RX-FIFO threshold (whatever I3C acts as controller/target) 0 (B_0x0): 1-byte threshold 1 (B_0x1): 1-word/4-bytes threshold |
| TXDMAEN | TX-FIFO DMA request enable (whatever I3C acts as controller/target) 0 (B_0x0): DMA mode is disabled for TX-FIFO 1 (B_0x1): DMA mode is enabled for TX-FIFO |
| TXFLUSH | TX-FIFO flush (whatever I3C acts as controller/target) 0 (B_0x0): no action 1 (B_0x1): flush TX-FIFO |
| TXTHRES | TX-FIFO threshold (whatever I3C acts as controller/target) 0 (B_0x0): 1-byte threshold 1 (B_0x1): 1-word / 4-byte threshold |
| SDMAEN | S-FIFO DMA request enable (when I3C acts as controller) 0 (B_0x0): DMA mode is disabled for reading status register I3C_SR 1 (B_0x1): DMA mode is enabled for reading status register I3C_SR |
| SFLUSH | S-FIFO flush (when I3C acts as controller) 0 (B_0x0): no action 1 (B_0x1): flush S-FIFO |
| SMODE | S-FIFO enable / status receive mode (when I3C acts as controller) 0 (B_0x0): S-FIFO is disabled 1 (B_0x1): S-FIFO is enabled. |
| TMODE | Transmit mode (when I3C acts as controller) 0 (B_0x0): C-FIFO and TX-FIFO are not preloaded before starting to emit a frame transfer. 1 (B_0x1): C-FIFO and TX-FIFO are first preloaded (also TX-FIFO if needed, depending on the frame format) before starting to emit a frame transfer. |
| CDMAEN | C-FIFO DMA request enable (when I3C acts as controller) 0 (B_0x0): DMA mode is disabled for C-FIFO 1 (B_0x1): DMA mode is enabled for C-FIFO |
| CFLUSH | C-FIFO flush (when I3C acts as controller) 0 (B_0x0): no action 1 (B_0x1): flush C-FIFO |
| TSFSET | Frame transfer set (software trigger) (when I3C acts as controller) 0 (B_0x0): no action 1 (B_0x1): setting this bit initiates a frame transfer by causing the hardware to assert the flag CFNFF in the I3C_EVR register (C-FIFO not full and a control word is needed) |