PS=B_0x0, TE=B_0x0, PCE=B_0x0, RXNEIE=B_0x0, MME=B_0x0, PEIE=B_0x0, CMIE=B_0x0, UESM=B_0x0, UE=B_0x0, TCIE=B_0x0, WAKE=B_0x0, IDLEIE=B_0x0, TXEIE=B_0x0, FIFOEN=B_0x0, RE=B_0x0
LPUART control register 1
| UE | LPUART enable 0 (B_0x0): LPUART prescaler and outputs disabled, low-power mode 1 (B_0x1): LPUART enabled |
| UESM | LPUART enable in low-power mode 0 (B_0x0): USART not able to wake up the MCU from low-power mode. 1 (B_0x1): USART able to wake up the MCU from low-power mode. |
| RE | Receiver enable 0 (B_0x0): Receiver is disabled 1 (B_0x1): Receiver is enabled and begins searching for a start bit |
| TE | Transmitter enable 0 (B_0x0): Transmitter is disabled 1 (B_0x1): Transmitter is enabled |
| IDLEIE | IDLE interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register |
| RXNEIE | Receive data register not empty 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): A LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register |
| TCIE | Transmission complete interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register |
| TXEIE | Transmit data register empty 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): A LPUART interrupt is generated whenever TXE =1 in the LPUART_ISR register |
| PEIE | PE interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register |
| PS | Parity selection 0 (B_0x0): Even parity 1 (B_0x1): Odd parity |
| PCE | Parity control enable 0 (B_0x0): Parity control disabled 1 (B_0x1): Parity control enabled |
| WAKE | Receiver wake-up method 0 (B_0x0): Idle line 1 (B_0x1): Address mark |
| M0 | Word length |
| MME | Mute mode enable 0 (B_0x0): Receiver in active mode permanently 1 (B_0x1): Receiver can switch between mute mode and active mode. |
| CMIE | Character match interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. |
| DEDT | Driver Enable deassertion time |
| DEAT | Driver Enable assertion time |
| M1 | Word length |
| FIFOEN | FIFO mode enable 0 (B_0x0): FIFO mode is disabled. 1 (B_0x1): FIFO mode is enabled. |