HDSEL=B_0x0, WUS1=B_0x0, CTSIE=B_0x0, OVRDIS=B_0x0, DEP=B_0x0, CTSE=B_0x0, DEM=B_0x0, WUFIE=B_0x0, TXFTCFG=B_0x0, TXFTIE=B_0x0, RXFTCFG=B_0x0, DDRE=B_0x0, WUS0=B_0x0, DMAT=B_0x0, RTSE=B_0x0, DMAR=B_0x0, RXFTIE=B_0x0, EIE=B_0x0
LPUART control register 3
| EIE | Error interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register. |
| HDSEL | Half-duplex selection 0 (B_0x0): Half-duplex mode is not selected 1 (B_0x1): Half-duplex mode is selected |
| DMAR | DMA enable receiver 0 (B_0x0): DMA mode is disabled for reception 1 (B_0x1): DMA mode is enabled for reception |
| DMAT | DMA enable transmitter 0 (B_0x0): DMA mode is disabled for transmission 1 (B_0x1): DMA mode is enabled for transmission |
| RTSE | RTS enable 0 (B_0x0): RTS hardware flow control disabled 1 (B_0x1): RTS output enabled, data is only requested when there is space in the receive buffer. |
| CTSE | CTS enable 0 (B_0x0): CTS hardware flow control disabled 1 (B_0x1): CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). |
| CTSIE | CTS interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register |
| OVRDIS | Overrun Disable 0 (B_0x0): Overrun Error Flag, ORE is set when received data is not read before receiving new data. 1 (B_0x1): Overrun functionality is disabled. |
| DDRE | DMA Disable on reception Error 0 (B_0x0): DMA is not disabled in case of reception error. 1 (B_0x1): DMA is disabled following a reception error. |
| DEM | Driver enable mode 0 (B_0x0): DE function is disabled. 1 (B_0x1): DE function is enabled. |
| DEP | Driver enable polarity selection 0 (B_0x0): DE signal is active high. 1 (B_0x1): DE signal is active low. |
| WUS0 | Wake-up from low-power mode interrupt flag selection 0 (B_0x0): WUF active on address match (as defined by ADD[7:0] and ADDM7) |
| WUS1 | Wake-up from low-power mode interrupt flag selection 0 (B_0x0): WUF active on address match (as defined by ADD[7:0] and ADDM7) |
| WUFIE | Wake-up from low-power mode interrupt enable 0 (B_0x0): Interrupt inhibited 1 (B_0x1): USART interrupt generated whenever WUF=1 in the LPUART_ISR register |
| TXFTIE | TXFIFO threshold interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. |
| RXFTCFG | Receive FIFO threshold configuration 0 (B_0x0): Receive FIFO reaches 1/8 of its depth. 1 (B_0x1): Receive FIFO reaches 1/4 of its depth. 3 (B_0x3): Receive FIFO reaches 3/4 of its depth. 4 (B_0x4): Receive FIFO reaches 7/8 of its depth. 5 (B_0x5): Receive FIFO becomes full. 6 (B_0x6): Receive FIFO reaches 1/2 of its depth. |
| RXFTIE | RXFIFO threshold interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. |
| TXFTCFG | TXFIFO threshold configuration 0 (B_0x0): TXFIFO reaches 1/8 of its depth. 1 (B_0x1): TXFIFO reaches 1/4 of its depth. 3 (B_0x3): TXFIFO reaches 3/4 of its depth. 4 (B_0x4): TXFIFO reaches 7/8 of its depth. 5 (B_0x5): TXFIFO becomes empty. 6 (B_0x6): TXFIFO reaches 1/2 of its depth. |