DLYBYP=B_0x0, CSHT=B_0x0, MTYP=B_0x0, FRCK=B_0x0, CKMODE=B_0x0
OCTOSPI device configuration register 1
| CKMODE | Clock mode 0/mode 3 0 (B_0x0): CLK must stay low while NCS is high (chip-select released). 1 (B_0x1): CLK must stay high while NCS is high (chip-select released). |
| FRCK | Free running clock 0 (B_0x0): CLK is not free running. 1 (B_0x1): CLK is free running (always provided). |
| DLYBYP | Delay block bypass 0 (B_0x0): The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral). 1 (B_0x1): The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. |
| CSHT | Chip-select high time 0 (B_0x0): NCS stays high for at least 1 cycle between external device commands. 1 (B_0x1): NCS stays high for at least 2 cycles between external device commands. 63 (B_0x3F): NCS stays high for at least 64 cycles between external device commands. |
| DEVSIZE | Device size |
| MTYP | Memory type 0 (B_0x0): Micron mode, D0/D1 ordering in DTR 8-data-bit mode. 1 (B_0x1): Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. 2 (B_0x2): Standard mode 3 (B_0x3): Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. 4 (B_0x4): HyperBus memory mode, the protocol follows the HyperBusless thansup> less than/sup>specification. 5 (B_0x5): HyperBus register mode, addressing register space. |