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stm32 /stm32h5 /STM32H533 /PSSI /PSSI_RIS

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Interpret as PSSI_RIS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)OVR_RIS

OVR_RIS=B_0x0

Description

PSSI raw interrupt status register

Fields

OVR_RIS

Data buffer overrun/underrun raw interrupt status

0 (B_0x0): No overrun/underrun occurred

1 (B_0x1): An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32