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stm32 /stm32h5 /STM32H533 /RCC /RCC_AHB4LPENR

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Interpret as RCC_AHB4LPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)OTFDEC1LPEN 0 (B_0x0)SDMMC1LPEN 0 (B_0x0)FMCLPEN 0 (B_0x0)OCTOSPI1LPEN

OCTOSPI1LPEN=B_0x0, SDMMC1LPEN=B_0x0, OTFDEC1LPEN=B_0x0, FMCLPEN=B_0x0

Description

RCC AHB4 sleep clock register

Fields

OTFDEC1LPEN

OTFDEC1 clock enable during Sleep mode

0 (B_0x0): OTFDEC1 peripheral clock disabled during Sleep mode

1 (B_0x1): OTFDEC1 peripheral clock enabled during Sleep mode (default after reset)
SDMMC1LPEN

SDMMC1 and SDMMC1 delay peripheral clock enable during Sleep mode

0 (B_0x0): SDMMC1 and SDMMC1 delay peripherals clock disabled during Sleep mode

1 (B_0x1): SDMMC1 and SDMMC1 delay peripherals clock enabled during Sleep mode (default after reset)
FMCLPEN

FMC clock enable during Sleep mode

0 (B_0x0): FMC peripheral clock disabled during Sleep mode

1 (B_0x1): FMC peripheral clock enabled during Sleep mode (default after reset)
OCTOSPI1LPEN

OCTOSPI1 clock enable during Sleep mode

0 (B_0x0): OCTOSPI1 peripheral clock disabled during Sleep mode

1 (B_0x1): OCTOSPI1 peripheral clock enabled during Sleep mode (default after reset)

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32