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stm32 /stm32h5 /STM32H533 /RCC /RCC_AHB4RSTR

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Interpret as RCC_AHB4RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)OTFDEC1RST 0 (B_0x0)SDMMC1RST 0 (B_0x0)FMCRST 0 (B_0x0)OCTOSPI1RST

SDMMC1RST=B_0x0, OTFDEC1RST=B_0x0, FMCRST=B_0x0, OCTOSPI1RST=B_0x0

Description

RCC AHB4 peripheral reset register

Fields

OTFDEC1RST

OTFDEC1 block reset

0 (B_0x0): does not reset OTFDEC1 block (default after reset)

1 (B_0x1): resets OTFDEC1 block
SDMMC1RST

SDMMC1 and SDMMC1 delay blocks reset

0 (B_0x0): does not reset SDMMC1 and SDMMC1 delay blocks (default after reset)

1 (B_0x1): resets SDMMC1 and SDMMC1 delay blocks
FMCRST

FMC block reset

0 (B_0x0): does not reset FMC block (default after reset)

1 (B_0x1): resets FMC block
OCTOSPI1RST

OCTOSPI1 block reset

0 (B_0x0): does not reset OCTOSPI1 block (default after reset)

1 (B_0x1): resets OCTOSPI1 block

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32