Regviz

stm32 /stm32h5 /STM32H533 /RCC /RCC_APB1HRSTR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RCC_APB1HRSTR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h5/STM32H523/RCC/RCC_APB1HRSTR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)UART9RST 0 (B_0x0)UART12RST 0 (B_0x0)DTSRST 0 (B_0x0)LPTIM2RST 0 (B_0x0)FDCANRST 0 (B_0x0)UCPD1RST

UART12RST=B_0x0, UART9RST=B_0x0, UCPD1RST=B_0x0, FDCANRST=B_0x0, LPTIM2RST=B_0x0, DTSRST=B_0x0

Description

RCC APB1 peripheral high reset register

Fields

UART9RST

UART9 block reset

0 (B_0x0): does not reset UART9 block (default after reset)

1 (B_0x1): resets UART9 block
UART12RST

UART12 block reset

0 (B_0x0): does not reset the UART12 block (default after reset)

1 (B_0x1): resets the UART12 block
DTSRST

DTS block reset

0 (B_0x0): does not reset the DTS block (default after reset)

1 (B_0x1): resets the DTS block
LPTIM2RST

LPTIM2 block reset

0 (B_0x0): does not reset the LPTIM2 block (default after reset)

1 (B_0x1): resets the LPTIM2 block
FDCANRST

FDCAN1 and FDCAN2 blocks reset

0 (B_0x0): does not reset the FDCAN1 and FDCAN2 blocks (default after reset)

1 (B_0x1): resets the FDCAN1 and FDCAN2 blocks
UCPD1RST

UCPD1 block reset

0 (B_0x0): does not reset the UCPD block (default after reset)

1 (B_0x1): resets the UCPD block

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32