I3C1EN=B_0x0, UART4EN=B_0x0, CECEN=B_0x0, SPI3EN=B_0x0, UART7EN=B_0x0, TIM12EN=B_0x0, TIM3EN=B_0x0, WWDGEN=B_0x0, USART11EN=B_0x0, CRSEN=B_0x0, USART2EN=B_0x0, I2C1EN=B_0x0, TIM6EN=B_0x0, USART6EN=B_0x0, UART5EN=B_0x0, TIM2EN=B_0x0, TIM5EN=B_0x0, SPI2EN=B_0x0, I2C2EN=B_0x0, USART10EN=B_0x0, USART3EN=B_0x0, TIM7EN=B_0x0, UART8EN=B_0x0, TIM4EN=B_0x0
RCC APB1 peripheral clock register
| TIM2EN | TIM2 clock enable 0 (B_0x0): TIM2 peripheral clock disabled (default after reset) 1 (B_0x1): TIM2 peripheral clock enabled |
| TIM3EN | TIM3 clock enable 0 (B_0x0): TIM3 peripheral clock disabled (default after reset) 1 (B_0x1): TIM3 peripheral clock enabled |
| TIM4EN | TIM4 clock enable 0 (B_0x0): TIM4 peripheral clock disabled (default after reset) 1 (B_0x1): TIM4 peripheral clock enabled |
| TIM5EN | TIM5 clock enable 0 (B_0x0): TIM5 peripheral clock disabled (default after reset) 1 (B_0x1): TIM5 peripheral clock enabled |
| TIM6EN | TIM6 clock enable 0 (B_0x0): TIM6 peripheral clock disabled (default after reset) 1 (B_0x1): TIM6 peripheral clock enabled |
| TIM7EN | TIM7 clock enable 0 (B_0x0): TIM7 peripheral clock disabled (default after reset) 1 (B_0x1): TIM7 peripheral clock enabled |
| TIM12EN | TIM12 clock enable 0 (B_0x0): TIM12 peripheral clock disabled (default after reset) 1 (B_0x1): TIM12 peripheral clock enabled |
| WWDGEN | WWDG clock enable 0 (B_0x0): WWDG peripheral clock disabled (default after reset) 1 (B_0x1): WWDG peripheral clock enabled |
| SPI2EN | SPI2 clock enable 0 (B_0x0): SPI2 peripheral clock disabled (default after reset) 1 (B_0x1): SPI2 peripheral clock enabled |
| SPI3EN | SPI3 clock enable 0 (B_0x0): SPI3 peripheral clock disabled (default after reset) 1 (B_0x1): SPI3 peripheral clock enabled |
| USART2EN | USART2 clock enable 0 (B_0x0): USART2 peripheral clock disabled (default after reset) 1 (B_0x1): USART2 peripheral clock enabled |
| USART3EN | USART3 clock enable 0 (B_0x0): USART3 peripheral clock disabled (default after reset) 1 (B_0x1): USART3 peripheral clock enabled |
| UART4EN | UART4 clock enable 0 (B_0x0): UART4 peripheral clock disabled (default after reset) 1 (B_0x1): UART4 peripheral clock enabled |
| UART5EN | UART5 clock enable 0 (B_0x0): UART5 peripheral clock disabled (default after reset) 1 (B_0x1): UART5 peripheral clock enabled |
| I2C1EN | I2C1 clock enable 0 (B_0x0): I2C1 peripheral clock disabled (default after reset) 1 (B_0x1): I2C1 peripheral clock enabled |
| I2C2EN | I2C2 clock enable 0 (B_0x0): I2C2 peripheral clock disabled (default after reset) 1 (B_0x1): I2C2 peripheral clock enabled |
| I3C1EN | I3C1 clock enable 0 (B_0x0): I3C1 peripheral clock disabled (default after reset) 1 (B_0x1): I3C1 peripheral clock enabled |
| CRSEN | CRS clock enable 0 (B_0x0): CRS peripheral clock disabled (default after reset) 1 (B_0x1): CRS peripheral clock enabled |
| USART6EN | USART6 clock enable 0 (B_0x0): USART6 peripheral clock disabled (default after reset) 1 (B_0x1): USART6 peripheral clock enabled |
| USART10EN | USART10 clock enable 0 (B_0x0): USART10 peripheral clock disabled (default after reset) 1 (B_0x1): USART10 peripheral clock enabled |
| USART11EN | USART11 clock enable 0 (B_0x0): USART11 peripheral clock disabled (default after reset) 1 (B_0x1): USART11 peripheral clock enabled |
| CECEN | HDMI-CEC clock enable 0 (B_0x0): HDMI-CEC peripheral clock disabled (default after reset) 1 (B_0x1): HDMI-CEC peripheral clock enabled |
| UART7EN | UART7 clock enable 0 (B_0x0): UART7 peripheral clock disabled (default after reset) 1 (B_0x1): UART7 peripheral clock enabled |
| UART8EN | UART8 clock enable 0 (B_0x0): UART8 peripheral clock disabled (default after reset) 1 (B_0x1): UART8 peripheral clock enabled |