PLL1RDY=B_0x0, HSION=B_0x0, PLL2ON=B_0x0, PLL3RDY=B_0x0, CSIRDY=B_0x0, HSI48ON=B_0x0, PLL1ON=B_0x0, HSEEXT=B_0x0, HSIDIVF=B_0x0, CSION=B_0x0, HSI48RDY=B_0x0, HSECSSON=B_0x0, CSIKERON=B_0x0, HSIDIV=B_0x0, PLL3ON=B_0x0, PLL2RDY=B_0x0, HSIKERON=B_0x0, HSIRDY=B_0x0, HSEON=B_0x0, HSEBYP=B_0x0, HSERDY=B_0x0
RCC clock control register
| HSION | HSI clock enable 0 (B_0x0): HSI is OFF 1 (B_0x1): HSI is ON (default after reset) |
| HSIRDY | HSI clock ready flag 0 (B_0x0): HSI clock is not ready (default after reset) 1 (B_0x1): HSI clock is ready |
| HSIKERON | HSI clock enable in Stop mode 0 (B_0x0): no effect on HSI (default after reset) 1 (B_0x1): HSI is forced to ON even in Stop mode |
| HSIDIV | HSI clock divider 0 (B_0x0): division by 1, hsi_ck, hsi_ker_ck = 64 MHz 1 (B_0x1): division by 2, hsi_ck, hsi_ker_ck = 32 MHz (default after reset) 2 (B_0x2): division by 4, hsi_ck, hsi_ker_ck = 16 MHz 3 (B_0x3): division by 8, hsi_ck, hsi_ker_ck = 8 MHz |
| HSIDIVF | HSI divider flag 0 (B_0x0): new division ratio not yet propagated to hsi_ck , hsi_ker_ck (default after reset) 1 (B_0x1): hsi_ck , hsi_ker_ck clock frequency reflects the new HSIDIV value (default register value when the clock setting is completed). |
| CSION | CSI clock enable 0 (B_0x0): CSI is OFF (default after reset) 1 (B_0x1): CSI is ON |
| CSIRDY | CSI clock ready flag 0 (B_0x0): CSI clock is not ready (default after reset) 1 (B_0x1): CSI clock is ready |
| CSIKERON | CSI clock enable in Stop mode 0 (B_0x0): no effect on CSI (default after reset) 1 (B_0x1): CSI is forced to ON even in Stop mode |
| HSI48ON | HSI48 clock enable 0 (B_0x0): HSI48 is OFF (default after reset) 1 (B_0x1): HSI48 is ON |
| HSI48RDY | HSI48 clock ready flag 0 (B_0x0): HSI48 clock is not ready (default after reset) 1 (B_0x1): HSI48 clock is ready |
| HSEON | HSE clock enable 0 (B_0x0): HSE is OFF (default after reset) 1 (B_0x1): HSE is ON |
| HSERDY | HSE clock ready flag 0 (B_0x0): HSE clock is not ready (default after reset) 1 (B_0x1): HSE clock is ready |
| HSEBYP | HSE clock bypass 0 (B_0x0): HSE oscillator not bypassed (default after reset) 1 (B_0x1): HSE oscillator bypassed with an external clock |
| HSECSSON | HSE clock security system enable 0 (B_0x0): CSS on HSE OFF (clock detector OFF) (default after reset) 1 (B_0x1): CSS on HSE ON (clock detector ON if the HSE oscillator is stable, OFF if not). |
| HSEEXT | external high speed clock type in Bypass mode 0 (B_0x0): HSE in analog mode (default after reset) 1 (B_0x1): HSE in digital mode |
| PLL1ON | PLL1 enable 0 (B_0x0): PLL1 OFF (default after reset) 1 (B_0x1): PLL1 ON |
| PLL1RDY | PLL1 clock ready flag 0 (B_0x0): PLL1 unlocked (default after reset) 1 (B_0x1): PLL1 locked |
| PLL2ON | PLL2 enable 0 (B_0x0): PLL2 OFF (default after reset) 1 (B_0x1): PLL2 ON |
| PLL2RDY | PLL2 clock ready flag 0 (B_0x0): PLL2 unlocked 1 (B_0x1): PLL2 locked |
| PLL3ON | PLL3 enable 0 (B_0x0): PLL3 OFF (default after reset) 1 (B_0x1): PLL3 ON |
| PLL3RDY | PLL3 clock ready flag 0 (B_0x0): PLL3 unlocked (default after reset) 1 (B_0x1): PLL3 locked |