PLL1SRC=B_0x0, PLL1RGE=B_0x0, PLL1REN=B_0x0, PLL1PEN=B_0x0, PLL1VCOSEL=B_0x0, PLL1QEN=B_0x0, PLL1M=B_0x0
RCC PLL clock source selection register
| PLL1SRC | PLL1M and PLLs clock source selection 0 (B_0x0): no clock send to PLL1M divider and PLLs (default after reset). 1 (B_0x1): HSI selected as PLL clock (hsi_ck) 2 (B_0x2): CSI selected as PLL clock (csi_ck) 3 (B_0x3): HSE selected as PLL clock (hse_ck) |
| PLL1RGE | PLL1 input frequency range 0 (B_0x0): PLL1 input (ref1_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL1 input (ref1_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz |
| PLL1FRACEN | PLL1 fractional latch enable |
| PLL1VCOSEL | PLL1 VCO selection 0 (B_0x0): wide VCO range: 192 to 836 MHz (default after reset) 1 (B_0x1): medium VCO range: 150 to 420 MHz |
| PLL1M | prescaler for PLL1 0 (B_0x0): prescaler disabled (default after reset) 1 (B_0x1): division by 1 (bypass) 2 (B_0x2): division by 2 3 (B_0x3): division by 3 32 (B_0x20): division by 32 63 (B_0x3F): division by 63 |
| PLL1PEN | PLL1 DIVP divider output enable 0 (B_0x0): pll1_p_ck output disabled (default after reset) 1 (B_0x1): pll1_p_ck output enabled |
| PLL1QEN | PLL1 DIVQ divider output enable 0 (B_0x0): pll1_q_ck output disabled (default after reset) 1 (B_0x1): pll1_q_ck output enabled |
| PLL1REN | PLL1 DIVR divider output enable 0 (B_0x0): pll1_r_ck output disabled (default after reset) 1 (B_0x1): pll1_r_ck output enabled |