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stm32 /stm32h5 /STM32H533 /RCC /RCC_PLL2DIVR

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Interpret as RCC_PLL2DIVR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL2N0 (B_0x0)PLL2P0 (B_0x0)PLL2Q0 (B_0x0)PLL2R

PLL2Q=B_0x0, PLL2R=B_0x0, PLL2P=B_0x0

Description

RCC PLL1 dividers register

Fields

PLL2N

Multiplication factor for PLL2VCO

3 (B_0x003): PLL2N = 4

4 (B_0x004): PLL2N = 5

5 (B_0x005): PLL2N = 6

128 (B_0x080): PLL2N = 129 (default after reset)

511 (B_0x1FF): PLL2N = 512
PLL2P

PLL2 DIVP division factor

0 (B_0x0): pll2_p_ck = vco2_ck

1 (B_0x1): pll2_p_ck = vco2_ck / 2 (default after reset)

2 (B_0x2): pll2_p_ck = vco2_ck / 3

3 (B_0x3): pll2_p_ck = vco2_ck / 4

127 (B_0x7F): pll2_p_ck = vco2_ck / 128
PLL2Q

PLL2 DIVQ division factor

0 (B_0x0): pll2_q_ck = vco2_ck

1 (B_0x1): pll2_q_ck = vco2_ck / 2 (default after reset)

2 (B_0x2): pll2_q_ck = vco2_ck / 3

3 (B_0x3): pll2_q_ck = vco2_ck / 4

127 (B_0x7F): pll2_q_ck = vco2_ck / 128
PLL2R

PLL2 DIVR division factor

0 (B_0x0): pll2_r_ck = vco2_ck

1 (B_0x1): pll2_r_ck = vco2_ck / 2 (default after reset)

2 (B_0x2): pll2_r_ck = vco2_ck / 3

3 (B_0x3): pll2_r_ck = vco2_ck / 4

127 (B_0x7F): pll2_r_ck = vco2_ck / 128

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32