PLL3SRC=B_0x0, PLL3PEN=B_0x0, PLL3REN=B_0x0, PLL3M=B_0x0, PLL3QEN=B_0x0, PLL3VCOSEL=B_0x0, PLL3RGE=B_0x0
RCC PLL clock source selection register
| PLL3SRC | PLL3M and PLLs clock source selection 0 (B_0x0): no clock send to PLL3M divider and PLLs (default after reset) 1 (B_0x1): HSI selected as PLL clock (hsi_ck) 2 (B_0x2): CSI selected as PLL clock (csi_ck) 3 (B_0x3): HSE selected as PLL clock (hse_ck) |
| PLL3RGE | PLL3 input frequency range 0 (B_0x0): PLL3 input (ref3_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL3 input (ref3_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz |
| PLL3FRACEN | PLL3 fractional latch enable |
| PLL3VCOSEL | PLL3 VCO selection 0 (B_0x0): wide VCO range 192 to 836 MHz (default after reset) 1 (B_0x1): medium VCO range 150 to 420 MHz |
| PLL3M | prescaler for PLL3 0 (B_0x0): prescaler disabled (default after reset) 1 (B_0x1): division by 1 (bypass) 2 (B_0x2): division by 2 3 (B_0x3): division by 3 32 (B_0x20): division by 32 63 (B_0x3F): division by 63 |
| PLL3PEN | PLL3 DIVP divider output enable 0 (B_0x0): pll3_p_ck output disabled (default after reset) 1 (B_0x1): pll3_p_ck output enabled |
| PLL3QEN | PLL3 DIVQ divider output enable 0 (B_0x0): pll3_q_ck output disabled (default after reset) 1 (B_0x1): pll3_q_ck output enabled |
| PLL3REN | PLL3 DIVR divider output enable 0 (B_0x0): pll3_r_ck output disabled (default after reset) 1 (B_0x1): pll3_r_ck output enabled |