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stm32 /stm32h5 /STM32H533 /RNG /RNG_SR

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Interpret as RNG_SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DRDY 0 (B_0x0)CECS 0 (B_0x0)SECS 0 (B_0x0)CEIS 0 (B_0x0)SEIS

CEIS=B_0x0, CECS=B_0x0, DRDY=B_0x0, SECS=B_0x0, SEIS=B_0x0

Description

RNG status register

Fields

DRDY

Data ready

0 (B_0x0): The RNG_DR register is not yet valid, no random data is available.

1 (B_0x1): The RNG_DR register contains valid random data.
CECS

Clock error current status

0 (B_0x0): The RNG clock is correct (fless thansub>RNGCLKless than/sub>> fless thansub>HCLKless than/sub>/32).

1 (B_0x1): The RNG clock is too slow (fless thansub>RNGCLKless than/sub>less than fless thansub>HCLKless than/sub>/32).
SECS

Seed error current status

0 (B_0x0): No faulty sequence has currently been detected.

1 (B_0x1): At least one of the following faulty sequences has been detected:
CEIS

Clock error interrupt status

0 (B_0x0): The RNG clock is correct (fless thansub>RNGCLKless than/sub>> fless thansub>HCLKless than/sub>/32)

1 (B_0x1): The RNG clock before the internal divider is detected too slow (fless thansub>RNGCLKless than/sub>less than fless thansub>HCLKless than/sub>/32)
SEIS

Seed error interrupt status

0 (B_0x0): No faulty sequence detected

1 (B_0x1): At least one faulty sequence is detected.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32