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stm32 /stm32h5 /STM32H533 /RTC /RTC_ALRMBSSR

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Interpret as RTC_ALRMBSSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SS0 (B_0x0)MASKSS0 (B_0x0)SSCLR

SSCLR=B_0x0, MASKSS=B_0x0

Description

RTC alarm B subsecond register

Fields

SS

Subseconds value
MASKSS

Mask the most-significant bits starting at this bit

0 (B_0x0): No comparison on subseconds for Alarm B.

1 (B_0x1): SS[31:1] are don’t care in Alarm B comparison.
SSCLR

Clear synchronous counter on alarm (Binary mode only)

0 (B_0x0): The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running.

1 (B_0x1): The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRBBINR.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32