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stm32 /stm32h5 /STM32H533 /SBS /SBS_CCCSR

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Interpret as SBS_CCCSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)EN1 0 (B_0x0)CS1 0 (B_0x0)EN2 0 (B_0x0)CS2 0 (B_0x0)RDY1 0 (B_0x0)RDY2

EN2=B_0x0, CS1=B_0x0, EN1=B_0x0, RDY2=B_0x0, RDY1=B_0x0, CS2=B_0x0

Description

SBS compensation cell for I/Os control and status register

Fields

EN1

enable compensation cell for VDDIO power rail

0 (B_0x0): I/O compensation cell disabled

1 (B_0x1): I/O compensation cell enabled
CS1

code selection for VDDIO power rail (reset value set to 1)

0 (B_0x0): Code from the cell (available in the SBS_CCVR)

1 (B_0x1): Code from SBS_CCCR
EN2

enable compensation cell for VDDIO2 power rail

0 (B_0x0): I/O compensation cell disabled

1 (B_0x1): I/O compensation cell enabled
CS2

code selection for VDDIO2 power rail (reset value set to 1)

0 (B_0x0): Code from the cell (available in SBS_CCVR)

1 (B_0x1): Code from SBS_CCCR
RDY1

VDDIO compensation cell ready flag

0 (B_0x0): VDDIO compensation cell not ready

1 (B_0x1): VDDIO compensation cell ready (code value provided by the cell can be used)
RDY2

VDDIO2 compensation cell ready flag

0 (B_0x0): VDDIO2 compensation cell not ready

1 (B_0x1): VDDIO2 compensation cell ready (code value provided by the cell can be used)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32