stm32 /stm32h5 /STM32H533 /SBS /SBS_CSLCKR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SBS_CSLCKR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LOCKSVTAIRCR 0 (B_0x0)LOCKSMPU 0 (B_0x0)LOCKSAU

LOCKSMPU=B_0x0, LOCKSAU=B_0x0, LOCKSVTAIRCR=B_0x0

Description

SBS CPU secure lock register

Fields

LOCKSVTAIRCR

VTOR_S and AIRCR register lock

0 (B_0x0): VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write enabled

1 (B_0x1): VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write disabled

LOCKSMPU

secure MPU registers lock

0 (B_0x0): Secure MPU registers writes enabled

1 (B_0x1): Secure MPU registers writes disabled

LOCKSAU

SAU registers lock

0 (B_0x0): SAU registers write enabled

1 (B_0x1): SAU registers write disabled

Links

()