DDR=B_0x0, BUSSPEED=B_0x0, NEGEDGE=B_0x0, SELCLKRX=B_0x0, WIDBUS=B_0x0, CLKDIV=B_0x000, HWFC_EN=B_0x0, PWRSAV=B_0x0
SDMMC clock control register
| CLKDIV | Clock divide factor 0 (B_0x000): SDMMC_CK frequency = sdmmc_ker_ck / 1 (Does not support DDR) 1 (B_0x001): SDMMC_CK frequency = sdmmc_ker_ck / 2 2 (B_0x002): SDMMC_CK frequency = sdmmc_ker_ck / 4 128 (B_0x080): SDMMC_CK frequency = sdmmc_ker_ck / 256 1023 (B_0x3FF): SDMMC_CK frequency = sdmmc_ker_ck / 2046 |
| PWRSAV | Power saving configuration bit 0 (B_0x0): SDMMC_CK clock is always enabled 1 (B_0x1): SDMMC_CK is only enabled when the bus is active |
| WIDBUS | Wide bus mode enable bit 0 (B_0x0): Default 1-bit wide bus mode: SDMMC_D0 used (Does not support DDR) 1 (B_0x1): 4-bit wide bus mode: SDMMC_D[3:0] used 2 (B_0x2): 8-bit wide bus mode: SDMMC_D[7:0] used |
| NEGEDGE | SDMMC_CK dephasing selection bit for data and command 0 (B_0x0): When clock division >1 (CLKDIV > 0) and DDR = 0: 1 (B_0x1): When clock division >1 (CLKDIV > 0) and DDR = 0: |
| HWFC_EN | Hardware flow control enable 0 (B_0x0): Hardware flow control is disabled 1 (B_0x1): Hardware flow control is enabled |
| DDR | Data rate signaling selection 0 (B_0x0): SDR Single data rate signaling 1 (B_0x1): DDR double data rate signaling |
| BUSSPEED | Bus speed for selection of SDMMC operating modes 0 (B_0x0): DS, HS, SDR12, SDR25, Legacy compatible, High speed SDR, High speed DDR bus speed mode selected 1 (B_0x1): SDR50, DDR50, SDR104, HS200 bus speed mode selected. |
| SELCLKRX | Receive clock selection 0 (B_0x0): sdmmc_io_in_ck selected as receive clock 1 (B_0x1): SDMMC_CKIN feedback clock selected as receive clock 2 (B_0x2): sdmmc_fb_ck tuned feedback clock selected as receive clock. |